1. Field of the Invention
The invention relates to a method for producing a semiconductor wafer and also to a method for processing a semiconductor wafer.
2. Background Art
Semiconductor wafers as substrates for particularly demanding components having ≦22 nm minimum structure length, that is to say the 22 nm Design Rule according to the ITRS (“International Technology Roadmap for Semiconductors”), have to be particularly flat. The flatness of previous wafers is limited by a decrease in thickness in the wafer edge region (“edge roll-off”) and by non-uniform material removal resulting from fluctuations in the local bond strength, e.g. on account of radially fluctuating dopant incorporation as early as during the crystal pulling process. These wafers are therefore unsuitable for ≦22 nm structures. What is essentially responsible for both effects is the chemical mechanical polishing process that is used at the end of each chain of process steps for producing substrate wafers according to the prior art in order to remove residual damage of the crystal structure of layers near the surface and to obtain a particularly low roughness.
In the prior art, the polishing process is carried out by relative movement between wafer and polishing pad under pressure, while supplying a polishing agent (slurry). The polishing agent usually contains colloidally dispersed silica sol in alkaline slurry, By contrast, the polishing pad contains no abrasive. The interplay between the mechanical grinding effect of the silica sol and the chemical attack of the alkaline polishing agent then effects material removal leading to the smoothing of the wafer surface.
Simultaneous chemical mechanical double-side polishing (DSP) is known in the prior art. In DSP, a plurality of semiconductor wafers are processed in material-removing fashion simultaneously on both sides between two colinear working disks. In this case, the working disks bear polishing pads which contain no substances with abrasive action, and a polishing agent containing substances with abrasive action is fed to the working gap formed between the working disks. Substances with abrasive action are characterized in that they are harder than the material of the workpiece. Silica sol (SiO2) is preferably used in DSP. SiO2 is harder than silicon. The silica sol is usually a colloid having grain sizes of the sol particles of between 5 nm and a few micrometers. During processing by DSP, one or a plurality of semiconductor wafers are inserted into a corresponding one or a plurality of thin guide cages that are moved by a rolling apparatus, which is formed from an inner and an outer toothed ring and which is arranged concentrically with respect to the working disks, in the working gap. The semiconductor wafers describe characteristic cycloidal trajectories on the surfaces of the working disks (planetary gear kinematics). Material removal is brought about by relative movement of polishing pad and semiconductor wafer under load and the frictional effect of the polishing agent.
One exemplary embodiment of DSP of silicon wafers is disclosed in US 2003/054650A. A suitable apparatus for such a DSP polishing process is presented in DE 100 07 390 A1. Suitable guide cages for the semiconductor wafers, so-called “carriers”, are described in EP 208 315 B1. Finally, a suitable polishing pad is known from U.S. Pat. No. 4,927,432.
The prior art likewise discloses a method called “Fixed-Abrasive Polishing” (FAP) for the planarization of “interlayer dielectrics” (ILD), in which a pad is used which has additives which come into contact with the surface to be processed and which are harder than the surface material thereby processed. This is described for example in WO 99/55491. An interlayer dielectric consists e.g. of a field oxide (soft silicon oxide) grown by deposition of e.g. TEOS (tetraethoxysilane) on a semiconductor structure in order to isolate different wiring layers from one another.
Likewise known is “Fixed-Abrasive Polishing (FAP) for the isolation of shallow trench isolation” (STI), e.g. described in US 2008/0153392 A1, in which a pad is likewise used which contains additives which come into contact with the surface to be processed and which are harder than the material of the processed workpiece surface, typically Si3N4 and various metals (Cu, MH 2.5; W, MH˜4) for electrical through-plating.
DE 10 2007 035 266 A1 discloses a method for polishing a substrate composed of semiconductor material comprising two-stage FAP polishing, wherein in a first step a polishing agent solution without abrasive substances and in a second step a polishing agent slurry with abrasive substances is brought between FAP polishing pad and substrate. The method can comprise an additional CMP step (pad without abrasives, polishing agent slurry with abrasives).
The abovementioned FAP methods are grinding methods, cf. U.S. Pat. No. 6,824,451 B2.
According to DIN 8580, “grinding” is understood to be a separating method in which the form of a workpiece is changed by eliminating the material cohesion by means of mechanical action at the processing location. A material particle removed by mechanical action is referred to as a chip. Examples of chip-removing processing methods include grinding, sawing, filing, cutting, turning, milling, drilling, planing and shearing. Grinding is distinguished from them in that the chipping takes place by means of a geometrically indeterminate cutting edge since many abrasive bodies are in engagement with random orientation of their cutting edges, whereas in the case of sawing, filing, turning, milling, drilling and planing, only one or a few cutting edges are in engagement with predetermined orientation with respect to the workpiece surface. A cutting edge that can change the material cohesion of the workpiece is distinguished by the fact that it is composed of a material that is harder than that of the workpiece.
In the prior art of FAP methods, the wear of the abrasive bodies results from microfracture, whereby new cutting edges are constantly produced, and from liberation of abrasive grain, whereby new layers of fresh abrasive grain are exposed. This mechanism is described for example in U.S. Pat. No. 6,824,451 B2. Grinding methods are distinguished by the fact that they produce crystal defects. These are brittle fracture crack systems, lattice dislocations, mosaics (small-angle grain boundaries), surface layers with amorphized structure, scratches, etc.
In chemical or chemical mechanical processing methods according to the prior art, the reaction of the etchant or polishing agent with the semiconductor surface brings about material removal. Examples of etchants include HF and HNO3 (acidic etching) or KOH, TMAH (tetramethylammonium hydroxide), NaOH etc. (alkaline etching). Polishing agents contain OH— as a reactant (alkaline silica sol). In this case, the reaction depends on the transport of the reactive starting substances within the etching or polishing liquid and to the semiconductor surface, on the temperature, on the concentration and, in particular, on the local material composition and on the material properties. Local material composition should be understood to mean the presence of oxides, metals or other materials alongside the semiconductor material used (e.g. silicon, germanium, III-V semiconductors, compound semiconductors). Material properties that influence the reaction are afforded for example by the presence of dopants and by the dopant concentrations.
Chemical mechanical polishing by means of silica sol known in the prior art brings about a material removal from the processed surface by means of a three-body interaction, namely between polishing pad, silica sol and the wafer surface. This three-body interaction has the effect that material removal is not effected in a path-determined manner, that is to say not exclusively along the path described by a point on the polishing pad over the workpiece surface, but rather is additionally determined by the dynamics of the silica sol particles in the polishing agent film established between pad and wafer surface; e.g. convection, turbulence, diffusion, etc. Non-path-determined processing is distinguished by the fact that the material removal is not deterministic, that is to say is determined only by the kinematics of the tool. This leads to an undesirably convex wafer form due to tapering of the wafer edge, owing to polishing agent depletion from the wafer edge to the wafer center or to locally preferential material removal at locations with chemically, structurally or electronically fluctuating properties.
The following are known in the prior art as further methods for processing semiconductor wafers in addition to those mentioned above:                two-disk or plane-parallel lapping (for short: lapping) using loose grain, e.g. disclosed in US 2004/0043709 A1;        plane-parallel grinding with lapping kinematics (Planetary Pad Grinding, PPG) using grain bonded in an easily changeable working layer (“abrasive pad”), e.g. explained in DE 10 2006 032 455 A1, suitable abrasive pads being described e.g. in U.S. Pat. No. 6,007,407 and U.S. Pat. No. 6,599,177 B2;        simultaneous double-side grinding between two colinearly arranged cup grinding disks (Double-Disk Grinding, DDG), e.g. explained in US 2003/0060050 A1;        Single-Side Grinding (SSG), also called surface rotation grinding, or Single-Side Fine-Grinding, SSFG), implemented as single-side processing step or processing step on both sides by means of sequential single-side processing of the front and rear sides of the semiconductor wafer, e.g. explained in EP 272 531 A1.        
In the prior art, the production of an always primarily convex wafer form cannot be avoided since the polishing agent always has to be fed to the working gap between wafer surface and pad surface via the edge of the wafer. A depletion of polishing agent therefore occurs from the edge to the center of the wafer. The material removal is thus greater at the edge than in the center of the wafer, which leads to an edge roll-off of the wafer thickness. In order that for future applications the wafer area can be used as intended (ITRS=“International Technology Roadmap for Semiconductors”) apart from an edge exclusion zone having a width of 1 mm, it should be endeavored to avoid such an edge roll-off if possible. The prior art still does not offer a convincing solution for this, on account of the problems outlined above.
It is furthermore known that during the pulling process, for example, dopant is incorporated with radially fluctuating density into the growing single crystal. This is described e.g. in W. Von Ammon: “Crystal Growth—From Fundamentals to Technology,” SILICON CRYSTAL GROWTH, 2004, p. 239-270. The radially fluctuating dopant concentration leads to correspondingly radially fluctuating electronic properties of the wafers produced from the single crystal by means of slicing. In subsequent processing steps for planarizing the wafer, the material removal mechanism of which is based on electronic interaction, therefore experience a removal rate that fluctuates radially in accordance with the dopant concentration. This includes all chemical and chemo-mechanical processing steps, in particular etching and chemical mechanical polishing using silica sol. The electronic and electrochemical interactions and removal mechanisms during etching or polishing are described e.g. in APPL. PHYS. A 60, 347-363 (1995).
Since etching and, in particular, chemical mechanical polishing are the final processing steps, which therefore crucially determine the form of the wafer, semiconductor wafers produced in accordance with the closest prior art always have a more or less pronounced radially symmetrical flat modulation of the surface. Such height modulations make semiconductor wafers produced according to the prior art unsuitable as substrates for particularly demanding semiconductor components. This is because the latter are distinguished by particularly thin vertical functional and separating layers. The production of these layers involves repeated use of polishing processes for creating planar interlayers during component production. In the case of an uneven starting surface, break through in the separating layers can occur during polishing. As a result, short circuits arise in the microelectronic components thus produced, which makes the latter unusable.
In contrast to etching or chemical mechanical polishing, grinding and lapping have none or only very little and harmlessly pronounced preferential material removal at electronically modulated regions, for the removal mechanism underlying these processes is a purely mechanical one by means of structural separation by chip removal: in the case of grinding by actual chipping by means of fixedly bonded abrasive, and in the case of lapping by brittle erosive structural fatigue by means of free grain in a slurry.